description package schematic symbol features absolute maximum ratings symbol value units peak off-state voltage v drm 1400 v peak reverse voltage v rrm -5 v off-state rate of change of voltage immunity dv/ dt 5000 v/usec continuous anode current at 110 o c i a110 32 a repetitive peak anode current (pulse width=1usec) i asm 4000 a rate of change of current di/ dt 150 ka/usec continuous gate-cathode voltage v gks +/-20 v peak gate-cathode voltage v gkm +/-25 v minimum negative gate-cathode voltage required for garanteed off-state v gk(off-min) -5 v maximum junction temperature t jm 150 o c maximum soldering temperature (installation) 260 o c this silicon power product is protected by one or more of the following u.s. patents: thinpak tm gate bond area gate return bond area anode bond area cathode bond area 5,446,316 5,557,656 5,564,226 5,517,058 4,814,283 5,135,890 5,521,436 5,585,310 5,248,901 5,366,932 5,497,013 5,532,635 5,105,536 5,777,346 5,446,316 5,577,656 5,473,193 5,166,773 5,209,390 5,139,972 5,103,290 5,028,987 5,304,847 5,569,957 4,958,211 5,111,268 5,260,590 5,350,935 5,640,300 5,184,206 5,206,186 5,757,036 5,777,346 5,995,349 4,801,985 4,476,671 4,857,983 4,888,627 4,912,541 5,424,563 5,399,892 5,468,668 5,082,795 4,980,741 4,941,026 4,927,772 4,739,387 4,648,174 4,644,637 4,374,389 4,750,666 4,429,011 5,293,070 this voltage controlled solidtron (vcs) discharge switch utilizes an n-type mos-controlled thyristor mounted on a thinpaktm, ceramic "chip-scale" hybrid. the vcs features the high peak current capability and low on- state voltage drop common to scr thyristors combined with extremely high di/dt capability. this semiconductor is intended for the control of high power circuits with the use of very small amounts of input energy and is ideally suited for capacitor discharge applications. the thinpak tm package is a perforated, metalized ceramic substrate attached to the silicon using 302 o c solder. an epoxy underfill is applied to protect the high voltage termination from debris. all exterior metal surfaces are tinned with 63pb/37sn solder providing the user with a circuit ready part. it's small size and low profile make it extremely attractive to high di/dt applications where stray series inductance must be kept to a minimum. l 1400v peak off-state voltage l 32a continuous rating l 4ka surge current capability l >100ka/usec di/dt capability l <100nsec turn-on delay l low on-state voltage l mos gated control l low inductance package anode (a) gate (g) cathode (k) gate return (gr) advanced pulse power device n- mos vcs, thinpak tm smct ta32n14a10
performance characteristics t j =25 o c unless otherwise specified measurements parameters symbol test conditions min. typ. max. units anode to cathode breakdown voltage v (br) v gk =-5, i a =1ma 1400 v anode-cathode off-state current i d v ge =-5v, v ak =1200v t c =25 o c <10 100 ua t c =150 o c 250 1000 ua gate-cathode turn-on threshold voltage v gk(th) v ak =v gk , i ak =1ma 0.7 v gate-cathode leakage current i gk(lkg) v gk =+/-20v 500 na anode-cathode on-state voltage v t i t =32a, v gk =+5v t c =25 o c 1.5 2.0 v (see figures 1,2 & 3) t c =150 o c 1.3 1.5 v input capacitance c iss 6 nf turn-on delay time t d(on) 0.2uf capacitor discharge 50 100 ns rate of change of current di/ dt t j =25 o c, v gk = -5v to +5v 75 ka/usec peak anode current i p v ak =800v, rg=4.7 w 3500 a discharge event energy e dis l s = 7nh (see figures 4,5 & 6) 32 mj turn-on delay time t d(on) 0.2uf capacitor discharge 50 100 ns rate of change of current di/ dt t j =150 o c, v gk = -5v to +5v 110 ka/usec peak anode current i p v ak =1200v, rg=4.7 w 4000 a discharge event energy e dis l s = 7nh (see figures 4,5 & 6) 70 mj junction to case thermal resistance r q jc anode (bottom) side cooled (note 1.) 0.08 o c/w junction to case thermal resistance r q jc cathode-gate (top) side cooled (note 2.) 1.5 o c/w notes: 1. case exterior assumed to be 0.002" of 63sn/37pb solder applied directly to anode. (see figure 7.) 2. case exterior assummed to be 0.002" of 63sn/37pb solder applied directly to cathode bond area of thinpak. (see figure 7.) typical performance curves (unless otherwise specified) figure 1. on-state characteristics figure 2. on-state characteristics figure 3. predicted high current on-state characteristics advanced pulse power device n- mos vcs, thinpak tm smct ta32n14a10
typical performance curves (continued) figure 4. turn-on delay characteristics figure 5. turn-on delay characteristics r g =4.7 w - 500 w , t j =25 o c r g =4.7 w & 50 w , t j =25 o c & 150 o c figure 6. 0.2uf discharge pulse performance characteristics (see figure 9.) figure 7. transient thermal impedance response advanced pulse power device n- mos vcs, thinpak tm smct ta32n14a10
typical performance curves (continued) figure 8. pulses to failure (pulse widths < 100usec) test circuit and waveforms figure 9. 0.2uf pulsed discharge circuit schematic figure 10. 0.2uf pulsed discharge circuit waveforms v gk v ak i a i p t d(on) 0 ref. 0 ref. 90% 10% di/dt - 10% to 50% of i a l the waveform shown is representative of one produced using a very low inductance circuit (<10nh). l v gk is held positive until i a oscillations have ended ( i a =0). supply voltage l series (total) dut r sense = 0.010 w c=0.2uf + - r g gate driver +5v -5v l l series(total) is caculated using 1 / (f 2 p ) 2 c where f = frequency of i a (see figure 10) l r sense is a calibrated current viewing resistor (cvr) advanced pulse power device n- mos vcs, thinpak tm smct ta32n14a10
application notes packaging and handling a1. junction temperature calculation the figure below shows a lump model of the thermal properties of the size 4 thinpak packaged vcs, from the 2-mil solder on the top of the lid on the left to the 2-mil solder on the bottom of the device on the right. by adding the user's lump model of the rest of the thermal system the user can calculate the junction and case temperature rise under any operating condition. a2. calculation of pulses to failure for intermediate/long pulse widths the user may calculate the number of pulses to failure (n f ) for long to intermedeiate pulse widths (not covered in the typical performance curve section) by applying the junction temperature rise (dt), calculated as described in a1, to the formula n f =(300/dt)9 . a3. use of gate return bond area. the mct was designed for high di/dt applications. an independent cathode connection or "gate return bond area" was provided to minimize the effects of rapidly changing anode-cathode current on the gate control voltage, (v=l*di/dt). it is therefore, critcal that the user utilize the gate return bond area as the point at which the gate driver reference (return) is attached to the vcs device. top cathode-gate bottom anode side anode (bottom) side interface cathode-gate (top) side interface 1. all metal surfaces are tinned using 63pb/37sn solder. 2. installation reflow temperature should not exceed 260 o c or internal package degradation may result. 3. package may be cooled from either top or bottom (see figures 7 & a1 application notes.) 4. as with all mos gated devices, proper handling procedures must be observed to prevent electrostatic discharge which may result in permanent damage to the gate of the device device junction package dimensions advanced pulse power device n- mos vcs, thinpak tm smct ta32n14a10
|
